A conventional random access memory (RAM) device must experience several delay stages before data stored therein may be recalled or supplied at an output of the memory device. For example, when an address value supplied to the memory device changes to a new address value, a conventional memory device must experience a first stage of delay associated with detecting the change in address and allowing the address to stabilize. After the change in address has been detected, a second stage of delay occurs while bit lines of a memory cell array are equalized, or precharged. This precharging imposes a predetermined voltage on the bit lines, and this predetermined voltage may later be influenced by the programming of specifically addressed memory cells. After the precharge stage of delay, a third stage of delay occurs while the precharge signals are deactivated and bit lines respond to a selected memory cell so that data corresponding to the programming of the addressed cell in the memory cell array appears at an input of a sense amplifier. Once sense amplifiers have sensed valid data on the bit lines, a fourth stage of delay occurs, which is associated with propagation delays of sense amplifiers and subsequent circuitry between the sense amplifiers and the output of the memory device, such as output buffers.
Moreover, in conventional memory devices, the precharge stage of delay consumes a constant period of time which is as short as possible. This precharge period is constant regardless of whether a prior memory access cycle was a read cycle or a write cycle and may occupy one fourth or more of an entire read access cycle. Furthermore, this precharge period is as short as possible because it occurs in series with other stages of delay which directly impact memory access time. However, when read cycles occur immediately following a write cycle, a stronger precharge is needed because full logic swings are conventionally developed on bit lines during a write cycle as opposed to small differential voltages which are developed on bit lines during a read cycle. Therefore, conventional memories utilize undesirably large precharge devices to accommodate this worst case situation where a read memory access cycle occurs immediately following a write memory access cycle.
Consequently, a need exists for a memory device in which a precharge stage occurs at the end of read and write cycles so that the precharge stage does not impact read access time of a subsequent memory read access cycle. Moreover, a need exists for a memory device in which a precharge stage occurs at the end of write cycles to accommodate a longer duration precharge time so that smaller precharge devices may be used.